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DATA SHEET
MOS INTEGRATED CIRCUIT
PD16432B
1/8, 1/15 DUTY LCD CONTROLLER/DRIVER
DESCRIPTION
The PD16432B is a controller/driver with 1/8 and 1/15 duty dot matrix LCD display capability. It has 60 segment outputs, 10 common outputs, and 5 dual segment/common outputs, giving a maximum display capability of 12 columns x 2 lines (at 1/15 duty). LED drive outputs, key scanning key source outputs, and key data inputs are also provided, making it ideal for use in a car stereo front panel, etc.
FEATURES
* Dot matrix LCD controller/driver * Pictograph display segment drive capability (max. 64) * LCD driver unit power supply VLCD independently settable (Max. 10 V) * On-chip key scan circuit (8 x 4 matrix) * Alphanumeric character and symbol display capability provided by on-chip ROM (5 x 7 dots) 240 characters + 16 user-defined characters * Display contents 1/8 duty: 13 columns x 1 line, 64 pictograph displays, 4 LEDs 1/15 duty: 12 columns x 2 lines, 60 pictograph displays, 4 LEDs * Serial data input/output (SCK, STB, DATA) * On-chip oscillator * Reduced power consumption possible using standby mode
ORDERING INFORMATION
Part Number Package 100-pin plastic QFP (0.5 pitch, 14 x 14), Standard ROM code
PD16432BGC-001-9EU
Document No. S11092EJ5V0DS00 (5th edition) Date Published April 1998 N CP(K) Printed in Japan
(c)
1998
PD16432B
BLOCK DIAGRAM
SEG61/COM14 SEG65/COM10
SEG1/KS1
SEG8/KS8 SEG9
SEG60
COM9
4 LED Driver 4 4-Bit LED Output Latch 4
5
5
Segment Driver 65
5
Common Driver 15
65-Bit Output Latch 65 2
15-Bit Shift Register
65-Bit Shift Register Timing Generator Parallel/Serial Conversion 5 5 8 OSCIN CG RAM 5x7 x 16 Display Data RAM 8 x 25 OSC Character Display RAM 64 Bits OSCOUT
CG ROM 5 x 7 x 240
8
5 STB SCK DATA Serial I/F Command Decoder Key Data RAM 4x8 KEY1 8
COM0
LED1
LED4
KEY4
KEY REQ
RESET LCD OFF SYNC
VLC1
VLC2
VLC3
VLC4
2
VLCD
VLC5
VDD
VSS
PD16432B
PIN CONFIGURATION
SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26
SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61/COM14 SEG62/COM13 SEG63/COM12 SEG64/COM11 SEG65/COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0
75 76
51 50
100 1
26 25
SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8/KS8 SEG7/KS7 SEG6/KS6 SEG5/KS5 SEG4/KS4 SEG3/KS3 SEG2/KS2 SEG1/KS1
LED1 LED2 LED3 LED4 VSS VLC5 VLC4 VLC3 VLC2 VLC1 VLCD VDD SYNC LCD OFF RESET KEY REQ SCK DATA STB OSCIN OSCOUT KEY1 KEY2 KEY3 KEY4
3
PD16432B
PIN DESCRIPTIONS
Pin Symbol SEG1/KS1 to SEG8/KS8 SEG9 to SEG60 SEG61/COM14 to SEG85/COM10 COM0 to COM9 LED1 to LED4 SCK Pin Name Segment output/key source output dual-function pins Segment outputs Segment output/common output dual-function pins Common outputs LED output pins Shift clock input Pin No. 26 to 33 Function Pins with dual function as dot matrix LCD segment outputs and key scanning key source outputs Dot matrix LCD segment outputs Switchable to either dot matrix LCD segment outputs or common outputs Dot matrix LCD common outputs LED outputs are Nch open-drain. Data shift clock Data is read on rising edge, and output on falling edge. Performs input of commands, key data, etc., and key data output. Input is performed from the MSB on the rise of the shift clock, and the first 8 bits are recognized as a command. Output is performed from the MSB on the fall of the shift clock. Output is Nch open-drain. Data input is enabled when "H". Command processing is performed on a fall. "H" if there is key data, "L" if there is none. Key data can be read irrespective of the state of this pin. Output is CMOS output. Initial state is set when "L". When "L", a forced LCD off operation is performed, and SEGn & COMn output the unselected waveform. Synchronization signal input/output pin. When 2 or more chips are used, wired-OR connection is made to each chip. A pull-up resistor is also required when one chip is used. Connect oscillator resistor.
34 to 85 86 to 90
91 to 100 1 to 4 17
DATA
Data input/output
18
STB
Strobe input
19
KEY REQ
Key request output
16
RESET LCD OFF
Reset input LCD off input
15 14
SYNC
Synchro
13
OSCIN OSCOUT KEY1 to KEY4 VDD VSS VLCD VLC1 to VLC5
Oscillation pins
20 21
Key data inputs Logic power supply pin GND pin LCD drive voltage pin LCD drive power supply
22 to 25 12 5 11 10 to 6
Key scanning key data inputs. Internal logic power supply pin GND pin LCD drive power supply pin Dot matrix LCD drive power supply
4
PD16432B
LCD DISPLAY
In the PD16432B LCD display, a 5 x 7-segment display and pictograph display segments can be driven. The pictograph display segment common output is allocated to COM0, and up to 64 can be driven. (1) Example of 1/8 duty connections
SEG 1 2 3 4 5 6 7 8 9 10 61 62 63 64 65
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM0
64 Pictograph Segments
(2) Example of 1/15 duty connections
SEG 1 2 3 4 5 6 7 8 9 10 56 57 58 59 60
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM0
60 Pictograph Segments
5
PD16432B
CHARACTER CODES AND CHARACTER PATTERNS
The relation between character codes and character patterns is shown below. Character codes 00H to 0FH are allocated to CGRAM. Character codes 10H to 1FH and E0H to FFH are undefined.
Higher Bits 0XH 1XH 2XH 3XH 4XH 5XH 6XH 7XH 8XH 9XH AXH BXH CXH DXH EXH FXH Lower Bits X0HRAM CG (1) CG (2) CG (3) CG (4) CG (5) CG (6) CG (7) CG (8) CG (9) CG (10) CG (11) CG (12) CG (13) CG (14) CG (15) CG (16)
X1HRAM
X2HRAM
X3HRAM
X4HRAM
X5HRAM
X6HRAM
X7HRAM
X8HRAM
X9HRAM
XAHRAM
XBHRAM
XCHRAM
XDHRAM
XEHRAM
XFHRAM
6
PD16432B
DISPLAY RAM ADDRESSES
Display RAM addresses are allocated as shown below irrespective of the display mode.
Column No. Line 1 Line 2 1 2 3 4 5 6 7 8 9 10 11 12 13
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H
PICTOGRAPH DISPLAY RAM ADDRESSES
Pictograph display RAM addresses are allocated as shown below.
Segment Output No. Address b7 00H 01H 02H 03H 04H 05H 06H 07H 1 9 17 25 33 41 49 57 b6 2 10 18 26 34 42 50 58 b5 3 11 19 27 35 43 51 59 b4 4 12 20 28 36 44 52 60 b3 5 13 21 29 37 45 53 61 b2 6 14 22 30 38 46 54 62 b1 7 15 23 31 39 47 55 63 b0 8 16 24 32 40 48 56 64
Note When 1/15 duty is used (12 columns x 2 lines), 61 to 64 are disabled.
7
PD16432B
CGRAM COLUMN ADDRESSES
A maximum of any sixteen 5 x 7-dot characters can be written in CGRAM. The row address within one character is allocated as shown below, and is specified by bits b7 to b5. The character code for which a write is to be performed must be specified beforehand with an address setting command.
Dot Data b7 0 0 0 0 1 1 1 b6 0 0 1 1 0 0 1 b5 0 1 0 1 0 1 0 b4 * * * * * * * b3 * * * * * * * b2 * * * * * * * b1 * * * * * * * b0 * * * * * * *
Row Address 00H 01H 02H 03H 04H 05H 06H
Row Address
Font Data (5 x 7 Dots)
* Font data (1: on, 0: off)
8
PD16432B
KEY MATRIX AND KEY DATA RAM CONFIGURATION The key matrix has an 8 x 4 configuration, as shown below.
KEY1 KEY2 = KEY3 KEY4 KS1 KS2 KS3 KS4 KS5 KS6 KS7 KS8
Key data is stored as shown below, and is read in MSB-first order by a read command.
b7 KS8 KS6 KS4 KS2 b4 b3 KS7 KS5 KS3 KS1 Read Order Key data is as follows: 1: On 0: Off b0
KEY4 KEY3 KEY2 KEY1
Key Input Equivalent Circuit
VDD Pull-Up Control Signal
R To Key Data RAM KEYn
In the event of key source output, the pull-up control signal becomes "H", and the pull-up transistor is turned on.
9
PD16432B
KEY REQUEST (KEY REQ)
A key request is output as shown below according to the state.
State In key scan operation KEY REQ
Note
Key Scan Internal Pull-Up Resistor During key scan : ON During display : OFF Always ON
High level is output while any key Note data is "1". High level is output in case of key input only. Fixed at low level
In standby mode or when SEGn & COMn are fixed at VLC5 When key scanning is stopped
Always OFF
Note KEY REQ does not become low until the key data is all "0". (It is not synchronized with the key data reads.)
LED OUTPUT LATCH CONFIGURATION
The low-order 4 bits of the LED output latch are enabled, and the high-order 4 bits disabled, as shown below.
MSB LSB
x
x
x
x
b3
b2
b1
b0
x : Don't Care
LED1 LED2 LED3 LED4
Latch data is as follows: 1: On 0: Off
10
PD16432B
COMMANDS
Commands set the display mode and status. The first byte after a rise edge on the STB pin is regarded as a command. If STB is driven low during command/data transfer, serial communication is initialized and the command/data being transferred is invalidated. (However, a command or data that has already been transferred is valid.) (1) Display Setting Command This command initializes the PD16432B
Note
, and sets the duty, number of segments, number of commons, master/
slave operation, and the drive voltage supply method. The state set when this command is executed is: LCD off, LED on, key scanning stopped. To restart the display, it is necessary to execute "status command" normal operation. However, nothing is done if the same mode is selected.
MSB 0 0 LSB
x
x
x
b2
b1
b0
x : Don't Care
Duty setting 0: 1/8 duty (SEG61/COM14 to SEG65/COM10 segment outputs) 1: 1/15 duty (SEG61/COM14 to SEG65/COM10 common outputs) Master/slave setting 0: Master 1: Slave Drive voltage supply method selection 0: External 1: Internal
After powering on
x
x
x
0
0
0
Note When multiple chips are used, only the chip that sent the command is enabled. If initialization is performed during display, the display may be affected (especially when multiple chips are used).
11
PD16432B
(2) Data Setting Command Sets the data write mode, read mode, and address increment mode.
MSB 0 1 LSB
x
x
b3
b2
b1
b0
x : Don't Care
Data write mode/read mode setting 000: Write to display data RAM 001: Write to character display RAM 010: Write to CGRAM 011: Write to LED output latch 100: Read key data Address increment mode setting (Display data RAM, character display RAM) 0: Increment after data write 1: Address fixed
After powering on
x
(3) Address Setting Command
x
0
0
0
0
Sets the display data RAM or character display RAM address.
MSB 1 0 LSB
x
b4
b3
b2
b1
b0
x:
Don't Care
Address : 00H to 18H Display data RAM Character display RAM : 00H to 07H : 00H to 0FH CGRAM After powering on
x
0
0
0
0
0
Note If an unspecified address is set, data cannot be written until a correct address is next set. The address is not incremented even in increment mode.
12
PD16432B
(4) Status Command Controls the status of the PD16432.
MSB 1 1 b5 b4 b3 b2 b1 LSB b0
LCD cotrol 00: LCD forced off (SEGn, COMn = VLC5) 01: LCD forced off (SEGn, COMn = unselected waveform) 10: Normal operation 11: Normal operation LED control 0: LED forced off 1: Normal operation Key scan control 0: Key scanning stopped 1: Key scan operation Standby mode setting 0: Normal operation 1: Standby mode Test mode setting 0: Normal operation 1: Test mode After powering on 0 0 0 0 0 0
Note
Note The following states are use prohibited modes, and key scanning does not operate if these states are set.
0 0 0 0 1 1 0 1 0 0 0 0
13
PD16432B
STANDBY MODE
If standby mode is selected with bit b4 of the status command, the following state is set irrespective of bits b3 to b0 of the status command. (1) LCD forced off (SEGn, COMn = VLC5) (2) LED forced off (3) Key scanning stopped (but KEYn = key input wait) (4) OSC stopped There are two ways of releasing standby mode, as follows: (1) Using Status Command Select normal operation with bit b4 of the status command. Example of Use of Status Command
Command/Data Item Standby mode Status command STB b7 L H 1 1 0 0 0 0 0 0 Standby release (OSC oscillation start), LCD control off (SEGn, COMn = VLC5), LED forced off, key scanning stopped 10 s 1 1 0 0 1 1 1 0
Note
Description b6 b5 b4 b3 b2 b1 b0
Standby transition time Status command End
L H L
Normal operation
Note If LCD normal operation or key scan operation is initiated within the standby transition time, the LCD may flicker.
14
PD16432B
(2) Using KEYn If any key is set to the ON state, the standby mode is released and OSC oscillation starts. Also, KEY REQ is set to "H", informing the microcomputer that a key has been pressed and standby mode has been released. In this state, the key data is not memorized, and therefore it is necessary to set key scanning to the normal state after the standby transition time, and fetch the key data. Example of Use of KEYn
Command/Data Item Standby mode Key data present STB b7 L L Standby release (KEY REQ = H, OSC oscillation start) 10 s 1 1 0 0 1 0 0 1
Note
Description b6 b5 b4 b3 b2 b1 b0
Standby transition time Status command
L H
LCD forced off (unselected waveform), LED forced off, key scan operation 1 frame or more
Key scan Data setting command Key data Key data Key data Key data End
L H H H H H L 0 * * * * 1 * * * * 0 * * * * 0 * * * * 0 * * * * 1 * * * * 0 * * * * 0 * * * *
Key data read, address increment For KS8, KS7 For KS6, KS5 For KS4, KS3 For KS2, KS1 Key distinction
Note If LCD normal operation or key scan operation is initiated within the standby transition time, the LCD may flicker.
15
PD16432B
SERIAL COMMUNICATION FORMATS
(1) Reception (Command/Data Write)
If data continues
STB
DATA
b7
b6
b5
b2
b1
b0
SCK
1
2
3
6
7
8
(2) Transmission (Command/Data Read)
STB
DATA
b7
b6
b5
b2
b1
b0
b7
b6
b5
b4
b3
SCK
1
2
3
6
7
8 1 s
1
2
3
4
5
6
Data Read Command Setting
Wait Time tWAIT
Data Read
Caution As the DATA pin is an Nch open-drain output, a pull-up resistor must be connected externally. (1 k to 10 k)
16
PD16432B
ABSOLUTE MAXIMUM RATINGS (TA = 25C, VSS = 0 V)
Parameter Logic supply voltage Logic input voltage Logic output voltage (Dout, LED) LCD drive supply voltage LCD drive power supply input voltage Driver output voltage (Segment, Common) LED drive current Package allowable dissipation Operating ambient temperature Storage temperature range Symbol VDD VIN VOUT VLCD VLC1 to VLC5 VOUT2 Rating -0.3 to +7.0 -0.3 to +VDD + 0.3 -0.3 to +7.0 -0.3 to +12.0 -0.3 to +VLCD + 0.3 -0.3 to +VLCD + 0.3 Unit V V V V V V
IOL1 PT TA Tstg
20 1000 -40 to +85 -55 to +150
mA mW C C
RECOMMENDED OPERATING RANGES
Parameter Logic supply voltage LCD drive supply voltage Logic input voltage Driver input voltage LED drive current Symbol VDD VLCD VIN VLCD1 to VLCD5 IOL1 MIN. 2.7 VDD 0 0 TYP. 5.0 8.0 MAX. 5.5 10.0 VDD VLCD 15 Unit V V V V mA
17
PD16432B
ELECTRICAL SPECIFICATIONS (UNLESS SPECIFIED OTHERWISE, TA = -40 to +85C, VDD = 5 V 10%, VLCD = 8 V 10%)
Parameter High-level input voltage Low-level input voltage High-level input current Low-level input current Low-level output voltage High-level output voltage Low-level output voltage High-level leak current Low-level leak current Common output ONresistance Segment output ONresistance Current consumption (Logic) Symbol VIH VIL IIH IIL VOL1 VOH2 VOL2 ILOH2 ILOL2 RCOM SCK, STB, LCDOFF, RESET, KEY1 to KEY4 SCK, STB, LCDOFF, RESET, KEY1 to KEY4 LED1 to LED4, IOL1 = 15 mA OSCOUT, KEY REQ, IOH2 = -1 mA DATA, OSCOUT, SYNC, IOL2 = 4 mA DATA, SYNC, VIN/OUT = VDD DATA, SYNC, VIN/OUT = VSS VLCD to VLC5 COM0 to COM14, | IO | = 100 A VLCD to VLC5 SEG1 to SEG60, | IO | = 100 A Normal operationNote, VI = VDD or VSS, fOSC = 250 kHz Standby mode, VI = VDD or VSS, fOSC stopped Normal operation, internal bias selected, no load Standby mode, internal bias used, no load 0.9 VDD 0.1 VDD 1 -1 2.4 Test Conditions MIN. 0.7 VDD 0 TYP. MAX. VDD 0.3 VDD 1 -1 1.0 Unit V V
A A
V V V
A A
k
RSEG
4.0
k
IDD1
500
A A A A
IDD2 Current consumption (Driver) ILCD1 ILCD2
5 1 000 5
Note Normal operation: VDD = 5 V, VLCD = 8 V Remarks TYP. values are reference values for TA = 25C.
18
PD16432B
SWITCHING SPECIFICATIONS (UNLESS SPECIFIED OTHERWISE, TA = -40 to +85C, VDD = VLCD = 5 V 10%, RL = 5 k, CL = 150 pF)
Parameter Oscillator frequency Output data delay time Output data delay time SYNC delay time Symbol fOSC tPZL tPLZ tDSYNC R = 100 k SCK DATA SCK DATA Test Conditions MIN. 175 TYP. 250 MAX. 325 100 300 1.5 Unit kHz ns ns
s
Note The time for one frame is found as follows. 1 frame = 1/fOSC x 128 clocks x duty number + 1/fOSC x 64 clocks If fOSC = 250 kHz and duty = 1/15, 1 frame = 4 s x 128 x 15 + 4 s x 64 = 7.94 ms
REQUIRED TIMING CONDITIONS (UNLESS SPECIFIED OTHERWISE, TA = -40 to +85C, VDD = 5 V 10%, VLCD = 8 V 10%, RL = 5 k, CL = 150 pF)
Parameter Clock frequency High-level clock pulse width Low-level clock pulse width Shift-clock cycle High-level shift clock pulse width Low-level shift clock pulse width Shift clock hold time Data setup time Data hold time STB hold time STB hold time Wait time SYNC removal time Standby transition time Reset pulse width Power-ON reset time Symbol fOSC tWHC tWLC tCYK tWHK tWLK tHSTBK tDS tDH tHKSTB tWSTB tWAIT tSREM tPSTB tWRS tPON RESET From Power-ON 8th SCK 9th SCK , in data read Test Conditions OSCIN external clock OSCIN external clock OSCIN external clock SCK SCK SCK STB SCK DATA SCK SCK DATA SCK STB MIN. 100 1 1 900 400 400 1.5 100 200 1 1 1 250 10 0.1 4 TYP. MAX. 500 5 5 Unit kHz
s s
ns ns ns
s
ns ns
s s s
ns
s s
CLK
19
PD16432B
OUTPUT LOAD CIRCUIT
VDD
5 k DATA 150 pF
SWITCHING SPECIFICATION WAVEFORM DIAGRAMS
1/fC tWHC
VIH OSCIN VIL tWLC
VIH STB
VIH VIL tHSTBK tHKSTB tWSTB
tCYK tWLK VIH SCK VIL tDS VIH VIL tDH tWLK
DATA
20
PD16432B
SWITCHING SPECIFICATION WAVEFORM DIAGRAMS
SYNC Timing (Master) One Frame fOSC tDSYNC SYNC tSREM One Frame SYNC Timing (Slave) One Frame One Frame
Internal Reset
SCK VIL
tPZL
tPLZ
DATA VOL2
RESET
RESET tWRE
21
PD16432B
OUTPUT WAVEFORMS
(1) 1/8 Duty (1/4 Bias: VLC2: VLC3)
* Key scan period 0 VLCD VLC1 VLC2 VLC4 VLC5 VLCD VLC1 VLC2 VLC4 VLC5 1 2 3 4 5 6 7 * K 0 1
COM0
COM1
COM7
VLCD VLC1 VLC2 VLC4 VLC5 VLCD VLC1 VLC2 VLC4 VLC5 VLCD VLC1 VLC2 VLC4 VLC5
SEG1
SEG2
VLCD 3/4VLCD SEG1-COM0 2/4VLCD 1/4VLCD 0 -1/4VLCD -2/4VLCD -3/4VLCD -VLCD VLCD 3/4VLCD SEG1-COM1 2/4VLCD 1/4VLCD 0 -1/4VLCD -2/4VLCD -3/4VLCD -VLCD
512 s 4.4 ms
256 s
22
PD16432B
Enlargement of Key Scan Period
7 1 VLCD VLC1 VLC2 VLC4 VLC5 VLCD VLC1 VLC2 VLC4 VLC5 VLCD VLC1 VLC2 VLC4 VLC5 2 3 4 K 5 6 7 8 0
COM0
SEG1
SEG2
SEG8
SEG9 to SEG65
VLCD VLC1 VLC2 VLC4 VLC5 VLCD VLC1 VLC2 VLC4 VLC5
= Key source output
23
PD16432B
(2) 1/15 Duty (1/5 Bias)
* Key scan period * 14 K 1 2
0 VLCD VLC1 VLC2 VLC3 VLC4 VLC5 VLCD VLC1 VLC2 VLC3 VLC4 VLC5
1
2
3
4
5
6
7
8
9
10
11
12
13
COM0 1/2VLCD
COM1 1/2VLCD
COM14 1/2VLCD
VLCD VLC1 VLC2 VLC3 VLC4 VLC5 VLCD VLC1 VLC2 VLC3 VLC4 VLC5 VLCD
SEG1
3/5VLCD 1/2VLCD 1/5VLCD SEG1-COM0 0 -1/5VLCD -1/2VLCD -3/5VLCD -VLCD 512 s 7.9 ms 256 s
24
PD16432B
Enlargement of Key Scan Period
14 1 VLCD VLC1 VLC2 VLC3 VLC4 VLC5 VLCD VLC1 VLC2 VLC3 VLC4 VLC5 VLCD VLC1 VLC2 VLC3 VLC4 VLC5 2 3 4 K 5 6 7 8 0
COM0 1/2VLCD
SEG1
SEG2
SEG8
VLCD VLC1 VLC2 VLC3 VLC4 VLC5 VLCD VLC1 VLC2 VLC3 VLC4 VLC5
SEG9 to SEG65
= Key source output
25
PD16432B
ACCESS PROCEDURES
Access procedures are illustrated below by means of flowcharts and timing charts. 1. Initialization (1) Flowchart
Start
Initial state initialization
Display setting command (command 1) MSB LSB 0 0 0 0 0 1 0 1 (1/15 duty, master, internal drive)
Key scan start
Status command (command 2) MSB 1 1 0 0 1 0 0
LSB 1 (LCD off, LED off, key scan operation)
Display data RAM write
Data setting command (command 3) MSB LSB 0 1 0 0 0 0 0 0 (Display data RAM, increment)
Address setting
Address setting command (command 4) MSB LSB 1 0 0 0 0 0 0 0 (Display data RAM: 0H)
Display data
All data written? YES Character display RAM write
NO
Data setting command (command 5) MSB LSB 0 1 0 0 0 0 0 1 (Character display RAM, increment)
Character data
All data written? YES
NO
26
PD16432B
LED output latch write
Data setting command (command 6) MSB LSB 0 1 0 0 0 0 1 1 (LED latch, increment)
LED data
LCD, LED on
Status command (command 7) MSB 1 1 0 0 1 1 1
LSB 0 (LCD on, LED on, key scan operation)
To next processing
(2) Timing chart
DATA SCK STB DATA SCK STB DATA SCK STB Data n Command 6 Data Command 7 Data n-1 Data n Command 5 Data 1 Command 1 Command 2 Command 3 Command 4 Data 1
27
PD16432B
2. Display Data Rewrite (Address Setting) (1) Flowchart
Start
Display data RAM write
Data setting command (command 1) MSB LSB 0 1 0 0 1 0 0 0 (Display data RAM, address fixed)
Address setting
Address setting command (command 2) MSB LSB 1 0 0 0 0 1 0 1 (Display data RAM: 5H)
Display data
To next processing
(2) Timing chart
DATA SCK STB Command 1 Command 2 Data
28
PD16432B
3. Key Data Read (1) Flowchart
Start
KEY REQ recognition
KEY REQ = H? YES
NO
Key data read
Data setting command (command 1) MSB LSB 0 1 0 0 0 1 0 0 (Key data)
Wait OK? YES
NO Wait time: 1 s
Key data
All data read? YES To next processing
NO
(2) Timing chart
DATA SCK STB KEY REQ Command 1 tWAIT Data 1 Data 2 Data 3
DATA SCK STB KEY REQ
Data 4
Cautions 1. Wait time tWAIT (1 s) is necessary from the rise of the 8th shift clock of command 1 until the fall of the 1st shift clock of data 1. 2. KEY REQ does not become low until the key data is all "0". (It is not synchronized with the key data reads.)
29
PD16432B
4. CGRAM Write (1) Flowchart
Start
CGRAM write
Data setting command (command 1) MSB LSB 0 1 0 0 0 0 1 0 (CGRAM, increment)
Address setting
Address setting command (command 2) MSB LSB 1 0 0 0 0 0 0 0 (CGRAM character code: 0H)
CGRAM data
All data written? YES To next processing
NO
(2) Timing chart
DATA SCK STB DATA SCK STB
Command 1
Command 2
Data 1
Data 2
Data 6
Data 7
30
PD16432B
5. Standby (Released by Status Command) (1) Flowchart
Start
Standby
Status command (command 1) MSB 1 1 0 1 0 0 0
LSB 0 (Standby)
Standby release
Status command (command 2) MSB 1 1 0 0 0 0 0
LSB 0 (Standby release)
Transition time OK? YES
NO Standby transition time: 10 s
Normal operation
Status command (command 3) MSB 1 1 0 0 1 1 1
LSB 0 (LCD on, LED on, key scan operation)
To next processing
(2) Timing chart
DATA SCK tSTBY STB Command 1 Command 2 Command 3
31
PD16432B
6. Standby (Released by KEYN) (1) Flowchart
Start
Standby
Status command (command 1) MSB 1 1 0 1 0 0 0
LSB 0 (Standby)
Key request
Key (KEYn) input KEY REQ = H, OSC oscillation start
Transition time OK? YES
NO Standby transition time: 10 s
Normal operation
Status command (command 2) MSB 1 1 0 0 1 1 1
LSB 0 (LCD on, LED on, key scan operation)
To next processing
(2) Timing chart
DATA SCK tSTBY STB KEY REQ Command 1 Command 2
32
PD16432B
PACKAGE INFORMATION (UNIT: mm)
100 PIN PLASTIC TQFP (FINE PITCH) (
A B
14)
75 76
51 50
detail of lead end
C D
S
100 1
26 25
F
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ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 16.00.2 14.00.2 14.00.2 16.00.2 1.0 1.0 0.22 +0.05 -0.04 0.10 0.5 (T.P.) 1.00.2 0.50.2 0.145 +0.055 -0.045 0.10 1.00.1 0.10.05 3 +7 -3 1.27 MAX. INCHES 0.6300.008 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.6300.008 0.039 0.039 0.0090.002 0.004 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.0060.002 0.004 0.039 +0.005 -0.004 0.0040.002 3 +7 -3 0.050 MAX. S100GC-50-9EU-1
Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition.
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PD16432B
REFERENCE DOCUMENTS
NEC Semiconductor Device Reliability/Quality Control System Semiconductor Device Mounting Technology Manual (IEI-1212) (C10535E)
34
PD16432B
[MEMO]
35
PD16432B
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96. 5

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